e5500 core the P5020 is based on the 64-bit e5500 power architecture ? core. the e5500 core uses a seven-stage pipeline for low latency response to unpredictable code execution paths, boosting its single-threaded performa nce. key features: ? supports up to 2.0 ghz core frequencies ? tightly-coupled low latency cache hierarchy: 32 kb i/d (l1), 512 kb l2 per core ? up to 2 mb of shared platform cache (l3) ? 3.0 dmips/mhz per core ? up to 64 gb of addressable memory space ? hybrid 32-bit mode to support legacy software and seamless transition to 64-bit architecture virtualization the P5020 in cludes support for hardware- assisted virtualization. the e5500 core offers an extra core privilege level (hypervisor). virtualization software for the p5 family includes kernel-based virtual machine (kvm), linux ? containers, freescale hypervisor and commercial virtualization software from green hills ? software and enea ? . qoriq communications platforms qoriq P5020/p5010 processors overview the qoriq p5 family delivers scalable 64-bit processing with single-, dual- and quad-core devices. with frequencies scaling up to 2.0 ghz, a tightly coupled cache hierarchy for low latency and integrated hardware acceleration, the P5020 (dual-core) and p5010 (single-core) devices are ideally suited for compute intensive, power- conscious control plane applications. target markets and applications the P5020 is designed for high- performance, power-constrained control plane applications and provides an ideal combination of core performance, integrated accelerators and advanced i/o required for the following compute-intensive applications: ? enterprise equipment: router, switch, services ? data center: server appliance, san storage controller, iscsi controller, fcoe bridging ? aerospace and defense ? industrial computing: single-board computers, test/measurement, robotics qoriq P5020/p5010 processors accelerators and memory control networking elements core complex (cpu, l2 and frontside corenet platform cache) basic peripherals and interconnect real-time debug 10 ge parse, classify, distribute security fuse processor security monitor 2x usb 2.0 esdhc queue mgr. buffer mgr. pattern match engine 2.0 security 4.0 frame manager serial rapidio ? mgr. raid 5/6 engine 1ge 1ge 1ge 1ge 1ge elbc sd/mmc 2x duart 2x i 2 c spi, gpio srio pcie/ srio pcie pcie rapidio message unit 2x dma pcie watchpoint cross trigger perf. monitor corenet trace aurora peripheral access management unit sata 2.0 sata 2.0 pamu pamu pamu pamu 18-lane 5 ghz serdes corenet coherency fabric power architecture ? e5500 core 512 kb backside l2 cache 32 kb d-cache 32 kb i-cache 1024 kb frontside corenet platform cache 64-bit ddr2/3 memory controller 1024 kb frontside corenet platform cache 64-bit ddr2/3 memory controller *only available on P5020 *only available on P5020 qoriq P5020/p5010 processors p5 family comparison chart P5020/p5010 p5040/p5021 cpu cores 2x 64-bit e5500, 1x (p5010) 4x 64-bit e5500, 2x (p5021) threads 2/1 (single thread per core) 4/2 (single thread per core) max core frequency 1.6 to 2.0 ghz 1.8 to 2.4 ghz l2 512 kb per core 512 kb per core l3/platform 2 mb (P5020)/1 mb (p5010) 2 mb (both p5040 and p5021) ddr i/f 2x 64-bit ddr3 (up to 1333 mt/s) 1x 64-bit ddr3 (p5010) 2x 64-bit ddr3 (up to 1600 mt/s) pci express ? 4x pcie v2.0 3x pcie v2.0 (incl. 1 x 8) gbe, 10 gbe 5x 1 gbe, 1x 10 gbe 10x 1 gbe, 2x 10 gbe srio 2x srio v2.1 (supports type 9 and 11 messaging) n/a serdes lanes 18 lanes 20 lanes package 1295-pin 37.5 x 37.5 mm fc-pbga 1295-pin 37.5 x 37.5 mm fc-pbga
P5020/p5010 features list two (P5020) or one (p5010) single threaded e5500 cores built on power architecture ? technology ? up to 2.0 ghz with 64-bit isa support (power architecture v2.06 compliant) ? three levels of instruction: user, supervisor, hypervisor ? hybrid 32-bit mode to support legacy software and transition to 64-bit architecture corenet platform cache (cpc) ? 2.0 mb configured as dual 1 mb blocks (1 mb only for p5010) hierarchical interconnect fabric ? corenet fabric supporting coherent and non-coherent transactions with prioritization and bandwidth allocation amongst corenet endpoints ? qman fabric supporting packet-level queue management and quality of service scheduling two 64-bit ddr3/3l sdram memory controllers with ecc and interleaving support ? up to 1333 mt/s ? memory pre-fetch engine dpaa incorporating acceleration for the following functions ? packet parsing, classification and distribution (fman) ? qman for scheduling, packet sequencing and congestion management ? hardware bman for buffer allocation and de-allocation ? cryptography acceleration (sec 4.2) at up to 40 gb/s ? regex pattern matching acceleration (pme 2.1) at up to 10 gb/s serdes ? 18 lanes at up to 5 gb/s ? supports sgmii, xaui, pcie rev1.1/2.0, sata ethernet interfaces ? one 10 gb/s ethernet macs ? 5x 1 gb/s ethernet macs high-speed peripheral interfaces ? four pci express 2.0 controllers ? two serial rapidio ? controllers/ports (srio port) v1.3-compliant with features of v2.1 ? two serial ata (sata 2.0) controllers additional peripheral interfaces ? two full-speed usb 2.0 controllers with integrated phy ? enhanced secure digital host controller (sd/mmc/emmc) ? enhanced serial peripheral interface ? four i 2 c controllers ? four uarts ? integrated flash controller supporting nand and nor flash dma ? dual four channel support for hardware virtualization and partitioning enforcement ? extra privileged level for hypervisor support qoriq trust architecture 1.1 ? secure boot, secure debug, tamper detection, volatile key storage dpaa hardware accelerators frame manager (fman) 12 gb/s classify, parse and distribute buffer manager (bman) 64 buffer pools queue manager (qman) up to 2 24 queues security (sec) 17 gb/s: 3 des, aes pattern matching engine (pme) 10 gb/s aggregate rapidio ? manager supports type 9 and type 11 messaging raid5/6 engine calculates parity for network attached storage and direct attached storage applications data path acceleration architecture (dpaa) the P5020 integrates qoriq dpaa, an innovative multicore infrastructure for scheduling work to cores (physical and virtual), hardware accelerators and network interfaces. the fman, a primary element of the dpaa, parses headers from incoming packets and classifies and selects data buffers with optional policing and congestion management. the fman passes its work to the qman, which assigns it to cores or accelerators with a multi- level scheduling hierarchy. the P5020 also offers accelerators for cryptography, enhanced regular expression pattern matching and raid5/6 offload. system peripherals and networking for networking, the fman supports one 10 gb/s and 5x 1 gb/s mac controllers that connect to phys, switches and backplanes over rgmii, sgmii and xaui. high-speed system expansion is supported through four pci express ? v2.0 controllers that support a variety of lane widths. other peripherals include sata, sd/mmc, i 2 c, uart, spi, nor/nand controller, gpio and dual 1333 mt/s ddr3/3l controllers. software and tool support ? enea: real-time operating system support and virtualization software ? green hills: comprehensive portfolio of software and hardware development tools, trace tools, real-time operating systems and virtualization software ? mentor graphics ? : commercial-grade linux solution ? qnx ? : real-time os and development tool support ? qoriq P5020 development system (P5020ds-pb) for more information, please visit freescale.com/qoriq freescale, the freescale logo and qoriq are trademarks of freescale semiconductor, inc., reg. u.s. pat. & tm off. corenet is a trademark of freescale semiconductor, inc. all other product or service names are the property of their respective owners. the power architecture and power.org word marks and the power and power.org logos and related marks are trademarks and service marks licensed by power.org. ? 2012, 2013 freescale semiconductor,inc. document number: qP5020fs rev 4
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